1. Field of the Invention
The invention is related to the field of communications, and in particular, to integrated circuits that process communication packets.
2. Statement of the Problem
Communications systems transfer information in packet streams. The packets in the streams each contain a header and a payload. The header contains control information, such as addressing or channel information, that indicate how the packet should be handled. The payload contains the information that is being transferred. Some packets are broken into segments for processing. The term xe2x80x9cpacketxe2x80x9d is intended to include packet segments. Some examples of packets include, Asynchronous Transfer Mode (ATM) cells, Internet Protocol (IP) packets, frame relay packets, Ethernet packets, or some other packet-like information block.
An integrated circuit known as a stream processor has been developed recently to address the special needs of packet communication networking. Traffic stream processors are designed to apply robust functionality to extremely high-speed packet streams. This dual design requirement is often in conflict because the high-speeds limit the level of functionality that can be applied to the packet stream.
Robust functionality is critical with today""s diverse but converging communication systems. Stream processors must handle multiple protocols and interwork between streams of different protocols. Stream processors must also ensure that quality-of-service constraints are met with respect to bandwidth and priority. Each stream should receive the bandwidth allocation and priority that is defined in corresponding service level agreements. This functionality must be applied differently to different streamsxe2x80x94possibly thousands of different streams.
To provide such functionality, a RISC-based core processor was developed with its own network-oriented instruction set. The instruction set is designed to accomplish common networking tasks in the fewest cycles. The core processor executes software applications built from the instruction set to apply the robust functionality to high-speed packet streams.
To determine how the packets should be handled, the core processor constantly correlates packets with their respective context information. The core processor then retrieves the correlated context information from off-chip memory. Typically, expensive off-chip memory systems are required to speed up this process. When handling multiple packets, the core processor must maintain the coherency of the context information as the context information changes in a pipe-lined processing environment. Given the high-speeds of the packet streams, this function places a heavy burden on the core processor and expends critical processing capacity. Instead of providing additional quality-of-service processing, the core processor spends time correlating packets with context information, retrieving the correlated context information, and maintaining the coherency of the context information.
The invention helps solve the above problems with an integrated circuit that processes communication packets and can function as a traffic stream processor. The integrated circuit uses co-processor circuitry to correlate packets with respective context information and transfer the correlated context information to an on-chip context buffer. Cheaper off-chip memory systems can be used for context information because the latency of context retrieval is hidden from the core processor. The co-processor circuitry also maintains the coherency of the context information by preventing multiple copies from existing. The processing capacity savings can be used to handle higher-speed streams or increase the available functionality.
The integrated circuit comprises co-processor circuitry and a core processor. The co-processor circuitry comprises context buffers and data buffers. The co-processor circuitry receives and stores one of the communication packets in one of the data buffers. The co-processor circuitry correlates the one communication packet with one of a plurality of channel descriptors. The co-processor circuitry associates the one data buffer with one of the context buffers holding the one channel descriptor to maintain the correlation between the one communication packet and the one channel descriptor. The co-processor circuitry prevents multiple valid copies of the one channel descriptor from existing in the context buffers. In some examples of the invention, this is accomplished by tracking a number of the data buffers associated with the one context buffer. The core processor executes a packet processing software application that directs the processor to process the one communication packet in the one data buffer based on the one channel descriptor in the one context buffer.
In some examples of the invention, the co-processor circuitry determines if the one channel descriptor already exists in the context buffers and is valid. If not, the co-processor circuitry transfers the one channel descriptor from off-chip memory to the one context buffer. If so, the co-processor circuitry does not transfer the one channel descriptor from the off-chip memory. The co-processor circuitry sets an in-use count and a validity indicator in response to transferring the one channel descriptor from the off-chip memory to the one context buffer. The in-use count tracks the number of the data buffers associated with the one context buffer. The validity indicator indicates that the one channel descriptor in the one context buffer is valid. The co-processor circuitry increments the in-use count if the one channel descriptor is already in the one context buffer and is valid. After processing by the core processor, the co-processor circuitry transfers the one communication packet from the one data buffer, and in response, decrements the in-use count. If none of the data buffers are associated with the one channel descriptor, the co-processor circuitry clears the validity indicator, and transfers the one channel descriptor to the off-chip memory.